The present invention relates to a method for developing a resist film for use in photolithography and a method for fabricating a semiconductor device using the developing method.
A photolithography process in conventional semiconductor fabrication includes: a process of applying a resist onto the principal surface of a semiconductor substrate (i.e., a wafer); an exposure process of burning a design pattern on the resist film; and a developing process of eluting a region exposed to light or a region not exposed to light so as to form a resist pattern.
A developing process generally uses a developing method in which a developer discharging nozzle supplies a developer from a given position onto the entire surface of a wafer with the wafer kept still or rotating. An example of such a method is a method of performing multi-stage development as disclosed in, for example, Japanese Unexamined Patent Publication No. 2003-7595 (hereinafter, referred to as Patent Literature).
In conventional multi-stage development, after a developing process, a developer is removed without the supply of a rinsing solution onto a wafer and then a developer is supplied again onto the wafer. This prevents generation of unwanted materials due to a concentration decrease of the developer caused by the rinsing solution after the first developing step and effectively eliminates unwanted materials with a developer which is supplied next.
The present inventors conducted various studies on a method for forming a resist pattern using conventional multi-stage development, to find the following problems. That is, in regions where resist patterns have different opening ratios, interaction of adjacent regions causes a size variation among openings. It is confirmed that this variation occurs especially in a region having a small opening ratio, e.g., a region where a contact hole is formed.
Specifically, as the size of semiconductor devices decreases, a demand for miniaturization in photolithography processes increases. In addition, various regions such as a memory region, a logic region and a pad electrode region are formed in a semiconductor chip. Resist patterns have different opening ratios among these regions, so that density variation occurs between the patterns. The opening ratio of a pattern herein is an area ratio of an opening with respect to a target region. Accordingly, a region where an opening having a large area per a unit area is formed, e.g., a region for an electrode pad, has a high opening ratio and a region where an opening having a small area per a unit area is formed, e.g., a region for contact holes, has a low opening ratio.
In particular, in a developing method in which a developer is applied onto a resist film in a still state, more specifically a developing method for developing a resist pattern using the multi-stage development disclosed in Patent Literature described above, it is necessary to rotate a wafer before a rinsing process for fling-off without drying a developer. Accordingly, the method is susceptible to the influence of density variation between patterns, resulting in a large variation in pattern size (which will be described later in detail).